Atsushi KUROKAWA


Signal Propagation Delay Model in Vertically Stacked Chips
Nanako NIIOKA Masayuki WATANABE Masa-aki FUKASE Masashi IMAI Atsushi KUROKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2614-2624
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
3-D ICdelaythrough silicon viasensitivity analysis
 Summary | Full Text:PDF(2.5MB)

An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies
Li DING Zhangcai HUANG Atsushi KUROKAWA Jing WANG Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/05/01
Vol. E97-A  No. 5  pp. 1059-1074
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
gate delayovershooting effectmultiple-input gatesnanometer technology
 Summary | Full Text:PDF(2.4MB)

A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect
Minglu JIANG Zhangcai HUANG Atsushi KUROKAWA Qiang LI Bin LIN Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/05/01
Vol. E94-A  No. 5  pp. 1201-1209
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
static timing analysisgate delayeffective capacitancenon-iterative
 Summary | Full Text:PDF(1MB)

Simple Analytical Formulas for Estimating IR-Drops in an Early Design Stage
Kazuyuki OOYA Yuji TAKASHIMA Atsushi KUROKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/09/01
Vol. E93-A  No. 9  pp. 1585-1593
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
IR-droppower-gridpower-ringdecoupling capacitanceresponse surface method
 Summary | Full Text:PDF(809.6KB)

Impact of Self-Heating in Wire Interconnection on Timing
Toshiki KANAMOTO Takaaki OKUMURA Katsuhiro FURUKAWA Hiroshi TAKAFUJI Atsushi KUROKAWA Koutaro HACHIYA Tsuyoshi SAKATA Masakazu TANAKA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 388-392
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
interconnectdelay variationparasitic resistancethermaltemperatureself-heatSoC
 Summary | Full Text:PDF(221.9KB)

An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
Tsuyoshi SAKATA Takaaki OKUMURA Atsushi KUROKAWA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO Koutaro HACHIYA Katsuhiro FURUKAWA Masakazu TANAKA Hiroshi TAKAFUJI Toshiki KANAMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3016-3023
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
low powerleakagegate delay modelvariation
 Summary | Full Text:PDF(1.1MB)

Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability
Yuji TAKASHIMA Kazuyuki OOYA Atsushi KUROKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 2962-2970
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Desing
Keyword: 
redundant viamanufacturing variabilityreliability
 Summary | Full Text:PDF(490.8KB)

Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model
Minglu JIANG Zhangcai HUANG Atsushi KUROKAWA Shuai FANG Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/10/01
Vol. E92-A  No. 10  pp. 2531-2539
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Nonlinear Problems
Keyword: 
static timing analysisgate delayeffective capacitanceThevenin model
 Summary | Full Text:PDF(454.9KB)

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
Takaaki OKUMURA Atsushi KUROKAWA Hiroo MASUDA Toshiki KANAMOTO Masanori HASHIMOTO Hiroshi TAKAFUJI Hidenari NAKASHIMA Nobuto ONO Tsuyoshi SAKATA Takashi SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4  pp. 990-997
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
SSTAoutputtransition timegate delay modelprocess variation
 Summary | Full Text:PDF(2.6MB)

Prevention in a Chip of EMI Noise Caused by X'tal Oscillator
Atsushi KUROKAWA Hiroshi FUJITA Tetsuya IBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4  pp. 1077-1083
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
EMIcrystal oscillatornoisedecoupling capacitor
 Summary | Full Text:PDF(645.6KB)

Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation
Toshiki KANAMOTO Shigekiyo AKUTSU Tamiyo NAKABAYASHI Takahiro ICHINOMIYA Koutaro HACHIYA Atsushi KUROKAWA Hiroshi ISHIKAWA Sakae MUROMOTO Hiroyuki KOBAYASHI Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3666-3670
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
interconnectdelay variationparasitic capacitanceSoC
 Summary | Full Text:PDF(433.5KB)

Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills
Atsushi KUROKAWA Akira KASEBE Toshiki KANAMOTO Yun YANG Zhangcai HUANG Yasuaki INOUE Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 847-855
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
dummy fillcapacitance extractioncapacitance formulainterconnect
 Summary | Full Text:PDF(507.9KB)

Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay
Zhangcai HUANG Atsushi KUROKAWA Yun YANG Hong YU Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 840-846
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
CMOS inverterovershooting effectdeep submicrontiming analysis
 Summary | Full Text:PDF(426.5KB)

Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays
Atsushi KUROKAWA Hiroo MASUDA Junko FUJII Toshinori INOSHITA Akira KASEBE Zhangcai HUANG Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 856-864
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
interconnectworst-case delaystatic timing analysisprocess variationcapacitance extraction
 Summary | Full Text:PDF(509.1KB)

Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance
Atsushi KUROKAWA Masanori HASHIMOTO Akira KASEBE Zhangcai HUANG Yun YANG Yasuaki INOUE Ryosuke INAGAKI Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3453-3462
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
capacitance formulacapacitance calculationcapacitance extractioninterconnect capacitance
 Summary | Full Text:PDF(1.1MB)

Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills
Atsushi KUROKAWA Toshiki KANAMOTO Tetsuya IBE Akira KASEBE Wei Fong CHANG  Tetsuro KAGE Yasuaki INOUE Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3471-3478
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
dummy metaldummy fillinterconnect capacitanceCMP
 Summary | Full Text:PDF(466.8KB)

Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
Zhangcai HUANG Atsushi KUROKAWA Jun PAN Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3367-3374
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Prediction and Analysis
Keyword: 
static timing analysisgate slewCMOS invertereffective capacitanceinterconnect loads
 Summary | Full Text:PDF(824.1KB)

Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm
Yun YANG Atsushi KUROKAWA Yasuaki INOUE Wenqing ZHAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3412-3420
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Power/Ground Network
Keyword: 
SLP algorithmGGA methodP/G network optimizationglobal optimum
 Summary | Full Text:PDF(472.5KB)

A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills
Atsushi KUROKAWA Toshiki KANAMOTO Akira KASEBE Yasuaki INOUE Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/11/01
Vol. E88-A  No. 11  pp. 3180-3187
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
dummy filldummy metalcapacitance extractioninterconnect capacitance
 Summary | Full Text:PDF(489.6KB)

A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads
Zhangcai HUANG Atsushi KUROKAWA Yasuaki INOUE Junfa MAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/10/01
Vol. E88-A  No. 10  pp. 2562-2569
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: 
Keyword: 
static timing analysisgate delayCMOS invertereffective capacitanceinterconnect loads
 Summary | Full Text:PDF(526.5KB)

Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances
Atsushi KUROKAWA Takashi SATO Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 2933-2941
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Parasitics and Noise
Keyword: 
on-chip inductanceparasitic extractionVLSI interconnectsinductance extraction
 Summary | Full Text:PDF(1.1MB)

Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects
Atsushi KUROKAWA Kotaro HACHIYA Takashi SATO Kazuya TOKUMASU Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A  No. 4  pp. 841-845
Type of Manuscript:  Special Section LETTER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
inductanceparasitic extractionVLSI interconnectgeometric mean distanceskin effect
 Summary | Full Text:PDF(1018.5KB)