Atsushi HIRAI


A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation
Toshinori HOSOKAWA Atsushi HIRAI Yukari YAMAUCHI Masayuki ARAI 
Publication:   
Publication Date: 2017/09/01
Vol. E100-D  No. 9  pp. 2118-2125
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
low powertest generationcapture safe test vectorstest vector synthesisunsafe faults
 Summary | Full Text:PDF(1.4MB)

Application of Circuit-Level Hot-Carrier Reliability Simulation to Memory Design
Peter M. LEE Tsuyoshi SEO Kiyoshi ISE Atsushi HIRAISHI Osamu NAGASHIMA Shoji YOSHIDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/04/25
Vol. E81-C  No. 4  pp. 595-601
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
hot-carrier degradationreliabilitydevice lifetimecircuit simulationSRAMDRAM
 Summary | Full Text:PDF(750KB)

A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM
Hideharu YAHATA Yoji NISHIO Kunihiro KOMIYAJI Hiroshi TOYOSHIMA Atsushi HIRAISHI Yoshitaka KINOSHITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 557-565
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
CMOShigh speedcache SRAMchip floor plansense amplifieroutput registersetup/hold time
 Summary | Full Text:PDF(633.1KB)