Amir Masoud GHAREHBAGHI


C Description Reconstruction Method from a Revised Netlist for ECO Support
Yusuke KIMURA Amir Masoud GHAREHBAGHI Masahiro FUJITA 
Publication:   
Publication Date: 2018/04/01
Vol. E101-A  No. 4  pp. 685-696
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
C reconstructionECOCEGISprogram synthesis
 Summary | Full Text:PDF(728.5KB)

Fast and Efficient Signature-Based Sub-Circuit Matching
Amir Masoud GHAREHBAGHI Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7  pp. 1355-1365
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
circuit matchingsignature-based matchingsimilarity detection
 Summary | Full Text:PDF(493.6KB)

Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model
Amir Masoud GHAREHBAGHI Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/04/01
Vol. E97-D  No. 4  pp. 852-863
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design error diagnosisdesign error correctionmicro architecture debuggingformal verificationprocessors
 Summary | Full Text:PDF(615.3KB)

Transaction Ordering in Network-on-Chips for Post-Silicon Validation
Amir Masoud GHAREHBAGHI Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2309-2318
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
post-silicon validationtransaction orderingnetwork-on-a-chip (NoC)system-on-a-chip (SoC)
 Summary | Full Text:PDF(673.5KB)