Akira TANABE

A 0.18-µm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO
Masayuki MIZUNO  Koichiro FURUTA  Takeshi ANDOH  Akira TANABE  Takao TAMURA  Hidenobu MIYAMOTO  Akio FURUKAWA  Masakazu YAMASHINA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/20
Vol. E80-C  No. 12  pp. 1560-1571
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
phase-locked loop,  low voltage,  low jitter,  fast-lock time, 
  Summary |  Full Text:PDF
0.15 µm CMOS Devices with Reduced Junction Capacitance
Akira TANABE  Kiyoshi TAKEUCHI  Toyoji YAMAMOTO  Takeo MATSUKI  Takemitsu KUNIO  Masao FUKUMA  Ken NAKAJIMA  Naoki AIZAKI  Hidenobu MIYAMOTO  Eiji IKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/03/20
Vol. E78-C  No. 3  pp. 267-273
Type of Manuscript: Special Section PAPER (Special Issue on Sub-1/4 Micron Device and Process Technologies)
Category: 
Keyword: 
CMOS,  EB lithography,  Ti salicide,  SPICE, 
  Summary |  Full Text:PDF