Akihiro SUDA

Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis
Akihiro SUDA Hideki TAKASE Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2498-2506
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
high-level synthesisarray partitioningbuffer managementPolyhedral Optimization
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